Essentials of Professional VLSI Digital Design

<p>Become an advanced user of Verilog/System-Verilog Hardware Description Language: Learn the key language syntax and practical usage scenarios, enabling students to create a functioning digital design, simulate the design and understand gate-level implementation of the design by synthesis using TSMC018 standard cell library. Assimilate the must-know concepts and good practices of digital design through 28 hours of lectures and 30 hours of well-structured labs/mini-projects in a professional VLSI development environment built around LINUX, Perl and ModelSim.</p> <p><strong>What are the objectives of this course?</strong></p> <p>Upon successful completion of the course, the student will:</p> <p>1 Have in-depth knowledge and reference examples on SystemVerilog coding constructs.</p> <p>2 Achieve deeper understanding of key aspects related to: RTL coding considerations, Clock requirements, Clock-gatingTiming analysis, Reset Synchronization, Finite State Machines, Power management</p> <p>3 Build sound awareness on the fundamentals of: Design for Test and Manufacturing (DFTM) Power-Performance-Area (PPA) trade-offs Bus Protocols and typical side-band signals, Industry standard IP MMR interfaces based on AMBA APB and AXI4-Lite protocols</p> <p>4 Obtain an overview of key aspects related to:Industry Standard IP and SOC design cycles, Gate Netlist generation flows’ Physical design flows</p> <p>5 Understand how to systematically plan, partition, implement the RTL and create simple testbenches for simulating/debugging small-medium size IP designs.</p> <p>6 Gain confidence with basic IP design through implementation and touch-testing of a hierarchical IP with AMBA APB MMR programming interface and asynchronous clock domains.</p> <p>7 Gain sound familiarity with operating in a professional VLSI development environment that includes LINUX OS,usage of Perl programming for automation and ModelSim for simulations</p> <p>8 Take away all the environment needed to conduct trial RTL implementation, simulations, synthesis and schematic analysis on his/her personal machine using the lab reference material and free EDA tool** installs. J</p> <p><strong>Who is it intended for?</strong></p> <p>Electronics Engineering graduate students with basic knowledge of digital design and some familiarity with Verilog coding, who want to explore the VLSI engineering field in detail, beyond the scope of their curriculum. VLSI Masters students and Professionals entering the VLSI design and verification field, who want to build their career based up on a solid foundation of must-know concepts and good practices adopted by leading VLSI product companies. VLSI enthusiasts who want to become self-sufficient with RTL coding and simulation using high quality reference/lab material and free EDA tools**. <br /><strong></strong></p> <p><strong>Requirements:</strong></p> <p><strong></strong>Pre-requisites for taking this course:</p> <p>a Bachelor degree Electronics Engineering.</p> <p>b Basic knowledge on fundamentals of digital design.</p> <p>c Some familiarity with Verilog RTL coding and UNIX basics will be helpful.</p>